The present invention relates to a channel check test system for checking the continuity of a channel in digital circuit multiplication equipment (hereinafter called xe2x80x9cDCMExe2x80x9d).
The DCME is known as an equipment for transmitting a voice signal over a telephone communication line with high efficiency using low rate encoding technique and a digital speech interpolation technique. In this DCME, a channel check test for checking existence or nonexistence of the continuity of a transmission channel is made.
A conventional channel check test system will be explained with reference to the drawings. FIG. 12 is a diagram showing the structure of the conventional channel check test system.
In FIG. 12, reference numerals 1 and 2 respectively designate a transmitting side DCME and a receiving side DCME. Reference numeral 3 designates an input signal nonlinear-quantized by an A-law or a xcexc-law and inputted to the transmitting side DCME 1. An input pattern generator 4 generates an input test pattern nonlinear-quantized by the A-law or the xcexc-law. An A-law input pattern data memory 4a stores input test pattern data nonlinear-quantized by the A-law. A xcexc-law input pattern data memory 4b accumulates input test pattern data nonlinear-quantized by the xcexc-law. Reference numeral 4c designates a selector. A test pattern insertion circuit 5 inserts an output signal of the input pattern generator 4 into a channel to be tested. An encoder 6 encodes an output signal of the test pattern insertion circuit 5 with high efficiency.
In this figure, a decoder 7 decodes the encoded signal. Reference numerals 8a and 8b respectively designate a decoded signal nonlinear-quantized by the A-law or the xcexc-law and outputted from the decoder 7, and an output signal nonlinear-quantized by the A-law or the xcexc-law from the receiving side DCME 2. An output pattern generator 9 generates an output test pattern nonlinear-quantized by the A-law or the xcexc-law. An A-law output pattern data memory 9a stores output test pattern data nonlinear-quantized by the A-law. A xcexc-law output pattern data memory 9b stores output test pattern data nonlinear-quantized by the xcexc-law. Reference numeral 9c designates a selector. A comparator 10 compares the decoded signal 8a and the output test pattern. A counter 11 counts the number of conformity bits of the output test pattern and the decoded signal 8a. A judging circuit 12 judges existence or nonexistence of the continuity of a channel on the basis of an output of the counter 11. Reference numeral 13 designates judged results. Reference numerals 14a, 14b, 14c and 14d designate companding law setting signals.
An operation of the above-mentioned conventional channel check test system will next be explained with reference to the drawings.
The operation of the conventional channel check test system with respect to an operated channel which is not being tested, i.e., a channel for transmitting a voice talking signal will first be explained.
An input signal 3 inputted to the transmitting side DCME 1 is provided to the encoder 6 without inserting the input test pattern into this signal in the test pattern insertion circuit 5 and is encoded with high efficiency. Output data of the encoder 6 are outputted to the receiving side DCME 2.
The input signal 3 is a PCM signal nonlinear-quantized by the A-law or the xcexc-law prescribed in ITU Recommendation G.711. When a companding law of the nonlinear quantization of the input signal 3 is the A-law, the companding law setting signal 14b is provided such that an operating mode of the encoder 6 is set to the A-law. In contrast to this, when the companding law of the input signal 3 is the xcexc-law, the companding law setting signal 14b is provided such that the operating mode of the encoder 6 is set to the xcexc-law.
In the receiving side DCME 2, the received output data of the encoder 6 are decoded in the decoder 7, and are outputted as an output signal 8b from the receiving side DCME 2. The output signal 8b from the receiving side DCME 2 is also a PCM signal nonlinear-quantized by the A-law or the xcexc-law. The companding law setting signal 14c is provided, and an operating mode of the decoder 7 is set such that the output signal 8b from the receiving side DCME 2 is set to a predetermined companding law (the A-law or the xcexc-law).
The operation of the conventional channel check test system with respect to the channel which is being tested will next be explained.
The input pattern generator 4 generates an input test pattern for checking the channel. The test pattern insertion circuit 5 outputs this input test pattern instead of the input signal 3 inputted to the transmitting side DCME 1 to the encoder 6. The encoder 6 encodes the input test pattern with high efficiency, and output data of the encoder 6 are outputted to the receiving side DCME 2.
It is necessary to set the companding law of the input test pattern outputted from the input pattern generator 4 in conformity with the companding law of the encoder 6. Therefore, one of output data of the A-law input pattern data memory 4a and output data of the xcexc-law input pattern data memory 4b is selected in the selector 4c in accordance with a companding law setting signal 14a and is made to be an output signal of the input pattern generator 4.
In the receiving side DCME 2, the received output data of the encoder 6 are decoded in the decoder 7. Each bit of a decoded signal 8a outputted from this decoder 7 is compared with the corresponding bit of an output signal of the output pattern generator 9 in the comparator 10. Output data of the output pattern generator 9 should be an expected pattern of the decoded signal obtained by firstly encoding the output signal of the input pattern generator 4 and secondly re-decoding this encoded signal.
It is necessary to set the companding law of the output test pattern outputted from the output pattern generator 9 in conformity with the companding law of the decoder 7. Therefore, one of output data of the A-law output pattern data memory 9a and the xcexc-law output pattern data memory 9b is selected in the selector 9c in accordance with a companding law setting signal 14d and is made to be an output signal of the output pattern generator 9.
Compared results of each bit outputted from the comparator 10 are inputted to the counter 11 and this counter 11 counts the number of nonconformity bits within a predetermined time. The counted number of nonconformity bits outputted from the counter 11 is inputted to the judging circuit 12. When the counted value exceeds a predetermined value, the judging circuit 12 judges that the continuity of the testing channel does not exist. In contrast to this, when the counted value does not exceed the predetermined value, the comparing circuit 12 judges that the continuity of the testing channel exists, and outputs results 13 of this judgment.
In the channel check test system constructed above, when plural coding systems (e.g., coding systems prescribed in ITU Recommendations G.726, G.728, G.729, etc.) are supported in the DCME, one of the solution for this case is to prepare an input test pattern and an output test pattern in accordance with the coding systems separately. However, when the input test pattern and the output test pattern are respectively prepared in accordance with the coding systems, a problem exists in that a circuit scale of the channel check test system is large-sized.
A system for checking continuity by using a tone signal as the input test pattern and monitoring a sign bit of an output of the decoder 7 within the receiving side DCME 2 is considered as a method able to be commonly used irrespective of the coding systems with a simple structure.
FIG. 13 is a diagram showing the structure of another conventional channel check test system shown in e.g. Japanese Patent Application Laid-Open No. 7-131832.
In FIG. 13, reference numerals 100, 101 and 102 respectively designate a frequency information detecting section, a sign bit and a delay circuit for delaying the sign bit 101 by a data amount for about a half period of an input digital tone signal. An exclusive OR circuit 103 inputs the sign bit 101 and the output of the delay circuit 102 thereto and calculates an exclusive OR. A nonconformity number integral period counter 104 determines the number of added data of an output of the exclusive OR circuit 103. A nonconformity number adding integrator 105 adds and integrates the output of the exclusive OR circuit 103 corresponding to the data amount determined by the nonconformity number integral period counter 104. A nonconformity number comparator 106 judges conformity or nonconformity with respect to a frequency of the input digital tone signal in accordance with an output of the nonconformity number adding integrator 105.
An operation of another conventional channel check test system will next be explained.
If the digital tone signal is a normal digital tone signal, the sign bit 101 continuously repeats xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d every half period. The frequency information detecting section 100 detects this continuous repetition of xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d as follows. Namely, the sign bit 101 is delayed by the half period in the delay circuit 102. The sign bit 101 and the output of the delay circuit 102 are inputted to the exclusive OR circuit 103. The exclusive OR circuit 103 calculates an exclusive OR of the sign bit 101 and the output of the delay circuit 102.
Thus, as shown by a numerical reference 114 of FIG. 14(e), all outputs of the exclusive OR circuit 13 show xe2x80x9c1xe2x80x9d when the digital tone signal is the normal digital tone signal. The outputs of this exclusive OR circuit 103 are added to each other by a data number designated by the nonconformity number integral period counter 104 by using the nonconformity number adding integrator 105. An output of the nonconformity number adding integrator 105 corresponds to a degree of the continuous repetition of xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d every half period of the sign bit 101. Then, frequency is inspected by inspecting the output of the nonconformity number adding integrator 105 by the nonconformity number comparator 106.
Since another conventional channel check test system is constructed as mentioned above, the continuity of a channel can be checked by a simple structure by detecting the periodic repetition of the sign bit.
However, there are the following problems when another conventional channel check test system having the above structure of FIG. 13 is applied to the DCME.
FIG. 15 is a block diagram showing an example in which another conventional channel check test system having the structure of FIG. 13 is applied to the DCME.
In FIG. 15, an internal operation of the transmitting side DCME 1 is the same as the internal operation of the transmitting side DCME 1 explained in the structure of FIG. 12. In contrast to this, in the receiving side DCME 2, an output signal nonlinear-quantized by the A-law or the xcexc-law from the decoder 7 is provided to a sign extracting section 108 and a sign bit 101 is extracted. The sign bit 101 is inputted to the frequency information detecting section 100 and existence or nonexistence of the continuity of a channel is judged by detecting periodic repetition of the sign bit 101. A detailed operation of this frequency information detecting section 100 is equal to that explained in the structure of FIG. 13.
In FIG. 15, for example, an operation of the channel check test system will be considered when both a companding law of the input signal 3 to the transmitting side DCME 1 and a companding law of the output signal 8b from the receiving side DCME 2 are the xcexc-law. In this case, it is necessary to operate the encoder 6 within the transmitting side DCME 1 and the decoder 7 within the receiving side DCME 2 by the xcexc-law. However, it is here supposed that the decoder 7 is operated erroneously by the A-law by an error in the companding law setting signal 14c. 
Assume that a series of signals as shown in a table of FIG. 16 is used as the input test pattern. The signal series shown in the table of FIG. 16 shows a tone signal having 500 Hz in frequency and 3 dBm0 in signal level (in the case of 8 kHz in sampling frequency).
Influences of the deterioration of a signal waveform on coding and decoding are neglected to simplify the explanation. If the channel check test system is set such that both the encoder 6 and the decoder 7 are correctly operated by the xcexc-law, the pattern of a decoded signal 8a outputted from the decoder 7 should be the same as an input test pattern shown in the table of FIG. 16. However, when the decoder 7 is incorrectly operated by the A-law by the error in the companding law setting signal 14c, the pattern of the decoded signal 8a outputted from the decoder 7 shows values in a table of FIG. 17.
The signal series shown in the table of FIG. 16 and the signal series shown in the table of FIG. 17 are different from each other. However, when only a sign bit is noticed, a period of the sign bit of the signal series in the table of FIG. 16 is equal to a period of the sign bit of the signal series shown in the table of FIG. 17. Further, the frequency information detecting section 100 for judging existence or nonexistence of the continuity of a channel by detecting periodic repetition of the sign bit should originally judge that the continuity does not exist when there is an error in setting of the companding law of the decoder 7. However, a problem exists in that the frequency information detecting section 100 judges that the continuity of the channel exists.
The above explanation is made with respect to the operation of the channel check test system when the companding law of the decoder 7 is set erroneously. However, there is also a similar problem in the operation of the channel check test system when the companding law of the encoder 6 is set erroneously.
To solve the above-mentioned problems, an object of this invention is to provide a channel check test system applicable to a DCME and able to perform a detecting operation including an error in setting of a companding law (A-law/xcexc-law) and able to be realized by a simple structure.
To achieve this object, a channel check test system according to this invention comprises a transmitting side DCME including an input pattern generator for generating a nonlinear quantized input test pattern; a test pattern insertion circuit for inserting an output signal of the input pattern generator into a channel to be tested; and an encoder for encoding an output signal of the test pattern insertion circuit with high efficiency; and a receiving side DCME including a decoder for decoding a received signal from the channel to be tested; a linear converting section for converting the decoded signal to a linear quantized PCM signal; an adder for adding a predetermined offset value to an output value of the linear converting section; a sign extracting section for extracting a sign from an output signal of the adder; a delay unit for delaying the extracted sign by a predetermined time; an exclusive OR arithmetic unit for performing an exclusive OR operation of the extracted sign and an output signal of the delay unit; a counter for counting the number of times of conformity in which an output value of the exclusive OR arithmetic unit is in conformity with a predetermined value; and a comparator for comparing a counted value of the counter and a predetermined threshold value and outputting judged results.
In the channel check test system according to this invention, the receiving side DCME includes a second comparator for comparing the output value of the linear converting section and a second predetermined threshold value instead of the adder and the sign extracting section; the delay unit delays an output signal of the second comparator by a predetermined time; and the exclusive OR arithmetic unit performs the exclusive OR operation of the output signal of the second comparator and the output signal of the delay unit.
Further, a channel check test system according to this invention comprises a transmitting side DCME including an input pattern generator for generating a nonlinear quantized input test pattern; a test pattern insertion circuit for inserting an output signal of the input pattern generator into a channel to be tested; and an encoder for encoding an output signal of the test pattern insertion circuit with high efficiency; and a receiving side DCME including a decoder for decoding a received signal from the channel to be tested; a linear converting section for converting the decoded signal to a linear quantized PCM signal; an adder for adding a predetermined offset value to an output value of the linear converting section; a zero crossing number calculating section for calculating a zero crossing number of an output value of the adder; a first comparator for comparing a value of the zero crossing number outputted from the zero crossing number calculating section and a first predetermined threshold value and outputting first compared result; a second comparator for comparing the value of the zero crossing number outputted from the zero crossing number calculating section and a second predetermined threshold value and outputting second compared result; and a judging circuit for judging existence or nonexistence of continuity of the channel to be tested on the basis of the first and second compared results.
In the channel check test system according to this invention, the receiving side DCME includes a zero crossing interval calculating section for calculating a zero crossing interval of an output value of the adder instead of the zero crossing number calculating section; the first comparator compares a value of the zero crossing interval outputted from the zero crossing interval calculating section and the first predetermined threshold value, and outputs the first compared results; and the second comparator compares the value of the zero crossing interval outputted from the zero crossing interval calculating section and the second predetermined threshold value, and outputs the second compared results.
In the channel check test system according to this invention, the receiving side DCME includes a level crossing number calculating section for calculating a level crossing number of the output value of the linear converting section instead of the adder and the zero crossing number calculating section; the first comparator compares a value of the level crossing number outputted from the level crossing number calculating section and the first predetermined threshold value, and outputs the first compared results; and the second comparator compares the value of the level crossing number outputted from the level crossing number calculating section and the second predetermined threshold value, and outputs the second compared results.
In the channel check test system according to this invention, the receiving side DCME includes a level crossing interval calculating section for calculating a level crossing interval of the output value of the linear converting section instead of the adder and the zero crossing number calculating section; the first comparator compares a value of the level crossing interval outputted from the level crossing interval calculating section and the first predetermined threshold value, and outputs the first compared results; and the second comparator compares the value of the level crossing interval outputted from the level crossing interval calculating section and the second predetermined threshold value, and outputs the second compared results.
Further, a channel check test system according to this invention comprises a transmitting side DCME including an input pattern generator for generating a nonlinear quantized input test pattern; a test pattern insertion circuit for inserting an output signal of the input pattern generator into a channel to be tested; and an encoder for encoding an output signal of the test pattern insertion circuit with high efficiency; and a receiving side DCME including a decoder for decoding a received signal from the channel to be tested; a linear converting section for converting the decoded signal to a linear quantized PCM signal; a zero crossing number calculating section for calculating a zero crossing number of an output value of the linear converting section; a level crossing number calculating section for calculating a level crossing number of the output value of the linear converting section; a subtracter for calculating the difference between the calculated zero crossing number and the calculated level crossing number; an absolute value circuit for calculating an absolute value of an output value of the subtracter; a comparator for comparing an output value of the absolute value circuit and a predetermined threshold value and outputting compared result; and a judging circuit for judging existence or nonexistence of continuity of the channel to be tested on the basis of the compared result.
In the channel check test system according to this invention, the receiving side DCME includes a zero crossing interval calculating section for calculating a zero crossing interval of the output value of the linear converting section and a level crossing interval calculating section for calculating a level crossing interval of the output value of the linear converting section instead of the zero crossing number calculating section and the level crossing number calculating section; and the subtracter calculates the difference between the calculated zero crossing interval and the calculated level crossing interval.
In the channel check test system according to this invention, the receiving side DCME further includes a signal intensity calculating section for calculating intensity of the output signal of the linear converting section; a signal intensity judging section including a fourth comparator for comparing the calculated signal intensity and a fourth predetermined threshold value and outputting fourth compared results, and a fifth comparator for comparing the calculated signal intensity and a fifth predetermined threshold value and outputting fifth compared results; and a judging circuit for judging existence or nonexistence of continuity of the channel to be tested on the basis of the all compared results.
In the channel check test system according to this invention, the receiving side DCME further includes a signal intensity calculating section for calculating intensity of the output signal of the linear converting section; and a signal intensity judging section including a fourth comparator for comparing the calculated signal intensity and a fourth predetermined threshold value and outputting fourth compared results, and a fifth comparator for comparing the calculated signal intensity and a fifth predetermined threshold value and outputting fifth compared results; and the judging circuit judges existence or nonexistence of continuity of the channel to be tested on the basis of the all compared results.
In the channel check test system according to this invention, the predetermined time in the delay unit is set to be a multiple of the time of a half period of the input test pattern.